Micro-processor based interlocking system (MPI) is a station automated control system intended to control the trains and shunting operation at station and adjoining hauls to meet the requirements of traffic safety.
UMBIS System Provides:
- process control of automation objects at station (core functions of electric switch and signal interlocking);
- automation objects’ status control at the station;
- provision of safe train movement;
- diagnostics of automation objects and self-diagnostics of system components;
- correlation with systems of the same or upper level (centralized traffic control system);
- archiving of information about the status of control objects, operator’s actions, operation diagnostics data component elements.
Control equipment level includes main and backup station operator’s AWPs as well as technician’s AWPs.
Integrity and confidentiality of the system information resources is ensured by restriction of unauthorized access to the AWPs and no possibility to make unauthorized changes in UMBIS working program.
Middle level is a hardware and software that ensures control of the main dependences of interlocking logic and sending control commands as well as provides communication between subsystems.
Middle level includes interlocking controllers and object controllers.
Lower level of the system includes trackside assets such as point machines, LED traffic lights, axle counting sensors, power supply racks, cables.
Advantages of the UMBIS System Implementation
The offered solutions allow easy and quick adaption of the system for use on the main and industrial railway transport lines.
Safety of micro-processor based interlocking system is achieved by means of hardware redundancy (MBIS controllers, interface loops) and the use of the control policy «2 of 3».
Reliability of the UMBIS is provided by hot redundancy of all nodes of the system and structural redundancy of communication channels.
Continuous monitoring and diagnostics of microelectronic devices’ state ensures timely detection and troubleshooting of pre-failure conditions.
The system features an effective surge protection, minimizing the impact of external interference on the microprocessor device.